The present invention relates generally to pipeline techniques in computer logic and, more particularly, to a design structure for dynamically adjusting pipelined data paths depending on the function/workload for improved power management.
Pipelining is a technique used in the design of microprocessors and other digital electronic devices to increase their performance. This technique generally refers to the concept of configuring various stages of logic in sequence, wherein data is initially introduced into the sequence of logic stages and then subsequently more data is introduced into the stages before completion of the operation on the first data through the sequence. Thus, pipelining reduces cycle time of a processor and hence increases instruction throughput, the number of instructions that can be executed in a unit of time. Pipelining came about sometime in the mid-1950's, when it was realized that most of the valuable circuitry of a computer was sitting idle during a computation. For example, after a memory fetch, the memory would be idle while the central processing unit (CPU) decoded an instruction, and after decode, the decode circuitry would sit idle during execution. After execution, still more idle time would result while the results were written into memory.
However, pipelines of large depths also have certain disadvantages associated therewith. For instance, when a program branches, the entire pipeline must be flushed. Also, the optimum pipelining depth varies for different classes of workloads. Where a particular function is not being repeated, no performance gain exists at that point by having multiple pipeline stages. Moreover, each stage of the pipeline is still individually clocked, thereby expending unnecessary power. Registers and corresponding clock trees are responsible for an increasingly large fraction of total gate count and power dissipation.
Accordingly, it would be desirable to be able to manage and adapt pipelined data paths to application requirements in order to efficiently cope with variability of data rates with respect to power dissipation.